I had already worked out what the VGA signals were on my DVK600 board (see previous post), so it was a simple matter to edit the supplied User Constraints File (.ucf) file for my hardware.
I tested the design against an old ViewSonic monitor I had laying around, and it worked. The characters were slightly clipped on the bottom and right edges, but until I test with more than one monitor I am going to blame the ViewSonic.
The VHDL code seemed to be pretty well structured, and I recommend you take a look if you need a VGA output or (like me) you are trying to learn VHDL by studying other's existing designs.
As a convenience, here is the edited portion of the original .ucf file to make it work with a "PS2 Keyboard + VGA Adapter" plugged into the "16I/Os 2" connector on a DVK600 with a Core3S500E daughter card plugged onto it.
#############################################################################
# Below was edited for DVK600 with VGA adapter board on 16I/Os_2
NET "i_clk" LOC = "P184" | IOSTANDARD = LVCMOS33 ;
NET "o_b" LOC = "p109" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "o_g" LOC = "p112" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "o_hsync" LOC = "p115" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "o_r" LOC = "p107" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "o_vsync" LOC = "p113" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "i_clk" TNM_NET = i_clk;
TIMESPEC TS_i_clk = PERIOD "i_clk" 20 ns HIGH 40%;
